Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | /VP | Control | Output | TTL, active low | Active low. Vector Pull. Goes low during an interrupt or reset vector fetch. On the NMOS 6502 this pin is VSS (ground). On a board that hardwires pin 1 to the ground plane, this output tries to drive high into ground every time it is released — the plane wins, large current flows, and the chip degrades or dies. WDC AN-002 says bend pin 1 outward before fitting to an Apple-1 or Apple II. |
| 2 | RDY | Control | Bidirectional | TTL | Ready. BIDIRECTIONAL on this part — the WAI instruction pulls it low to wait for an interrupt. On the NMOS 6502 RDY is input-only. Later TSMC-fabbed parts dropped the internal pull-up, so RDY may need an external pull-up. |
| 3 | PHI1O | Clock / Timing | Output | TTL clock | Phase 1 clock output. The inverted system clock for external timing. |
| 4 | /IRQ | Control | Input | TTL, active low | Active low. Interrupt Request. Maskable interrupt input. |
| 5 | /ML | Control | Output | TTL, active low | Active low. Memory Lock. Goes low during a read-modify-write cycle to signal that the bus is locked. On the NMOS 6502 this pin is NC. On an Apple-1, where pin 5 was wired as 6800-style VMA, AN-002 says bend this one outward too. |
| 6 | /NMI | Control | Input | TTL, active low | Active low. Non-Maskable Interrupt. Non-maskable interrupt input. |
| 7 | SYNC | Control | Output | TTL | Sync. Goes high during an opcode fetch cycle. Useful for single-stepping. |
| 8 | VDD | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. BE (pin 36) can be tied directly here. |
| 9 | A0 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 0. The address bus is contiguous: A0-A15 on pins 9-20 and 22-25. |
| 10 | A1 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 1. |
| 11 | A2 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 2. |
| 12 | A3 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 3. |
| 13 | A4 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 4. |
| 14 | A5 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 5. |
| 15 | A6 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 6. |
| 16 | A7 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 7. |
| 17 | A8 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 8. |
| 18 | A9 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 9. |
| 19 | A10 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 10. |
| 20 | A11 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 11. |
| 21 | VSS | Ground | Power | 0 V | Ground. Note: on the NMOS 6502, pin 1 is VSS and pin 21 is A11. Here pin 1 is /VP and pin 21 is VSS — the ground moved. |
| 22 | A12 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 12. |
| 23 | A13 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 13. |
| 24 | A14 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 14. |
| 25 | A15 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 15, the most significant address line. |
| 26 | D7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 7. The data bus is contiguous: D7 down to D0 on pins 26-33. |
| 27 | D6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 6. |
| 28 | D5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 5. |
| 29 | D4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 4. |
| 30 | D3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 3. |
| 31 | D2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 2. |
| 32 | D1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 1. |
| 33 | D0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 0. |
| 34 | R/W | Control | Output | TTL | Read / Write. High reads, low writes. The internal slash is NOT an active-low marker. |
| 35 | NC | No Connect | Not connected | No connect | No connect. |
| 36 | BE | Control | Input | TTL, active high | Bus Enable. ACTIVE HIGH. Must be tied HIGH — WDC confirms tying it directly to VDD (pin 8) is validated. Left floating the address bus may not be driven at all. On the NMOS 6502 this pin is NC. |
| 37 | PHI2 | Clock / Timing | Input | TTL clock | Phase 2 clock input. The system clock for bus timing. |
| 38 | /SO | Control | Input | TTL, active low | Active low. Set Overflow. A negative edge sets the V flag in the status register directly, without an interrupt. |
| 39 | PHI2O | Clock / Timing | Output | TTL clock | Phase 2 clock output. The system clock for external timing, in phase with PHI2 (pin 37). |
| 40 | /RES | Control | Input | TTL, active low | Active low. Reset. Held low for at least two clock cycles to reset the CPU. |
Common uses and repair diagnostics
The WDC W65C02S is the CMOS 6502 that people actually buy today to repair or rebuild 6502 machines. It is fully static (the clock can be stopped), draws microamps at idle, runs to 14 MHz, and replaces the NMOS illegal opcodes with real instructions. It adds the WAI (Wait for Interrupt) and STP (Stop) instructions, and its RDY pin is bidirectional — the WAI instruction pulls it low, where the NMOS 6502 RDY is input-only. Later TSMC-fabbed parts dropped the internal pull-up on RDY. The headline is that the "drop-in 6502" claim is false. THREE pins differ from the NMOS 6502, and one of them is dangerous. WDC prints these signals with a trailing "B" for "bar" — VPB, IRQB, MLB, NMIB, RWB, SOB, RESB — but this library uses a leading-slash convention (/VP, /IRQ, /ML, /NMI, R/W, /SO, /RES) instead. Say so once here so a reader holding the WDC datasheet can map between the two.
The WDC W65C02S is the CMOS 6502 that people actually buy today to repair or rebuild 6502 machines. It is fully static (the clock can be stopped), draws microamps at idle, runs to 14 MHz, and replaces the NMOS illegal opcodes with real instructions. The indexed-indirect JMP (a,x) mode is added, and the NMOS JMP ($xxFF) page-wrap bug is fixed. WAI (Wait for Interrupt) and STP (Stop) are WDC-only additions. Its RDY pin is bidirectional — the WAI instruction pulls it low — where the NMOS 6502 RDY is input-only. Later TSMC-fabbed parts dropped the internal pull-up on RDY.
The headline is that the "drop-in 6502" claim is false. THREE pins differ from the NMOS 6502, and one of them is dangerous: - Pin 1: VSS (ground) on the 6502, but /VP (Vector Pull, an OUTPUT) here. On a board that hardwires pin 1 to the ground plane, this output tries to drive high into ground every time it is released. The plane wins, large current flows through the output transistor, and the chip degrades or dies. WDC's own application note AN-002 tells you to bend pin 1 outward before fitting the chip to an Apple-1 or Apple II. That is the fix — lead with it. - Pin 5: NC on the 6502, /ML (Memory Lock, an output) here. AN-002 says bend this one outward too on an Apple-1, where pin 5 was wired as 6800-style VMA. - Pin 36: NC on the 6502, BE (Bus Enable, an input) here. It must be tied HIGH — WDC confirms tying it directly to VDD (pin 8) is validated. Left floating the address bus may not be driven at all.
The R65C02, R6502 and G65SC02 in 40-pin DIP ARE pin compatible with the NMOS 6502; it is specifically the WDC part that adds /VP on pin 1. Worth stating, because it explains why some people report a successful swap and others kill a chip.
Still in production, which makes it the practical choice for new 6502 designs and for replacing a failed NMOS 6502 where you control the board. The swap needs pin 1, 5 and 36 attention — say that on both this page and the 6502 page.
- Before fitting to an Apple-1 or Apple II, bend pin 1 (/VP) and pin 5 (/ML) outward — WDC AN-002 says so. Pin 1 driving into the ground plane will degrade or kill the chip.
- Tie pin 36 (BE) directly to VDD (pin 8). Left floating the address bus may not be driven at all.
- If RDY (pin 2) floats, later TSMC-fabbed parts dropped the internal pull-up — add an external pull-up.
- Do not assume a W65C02S is a drop-in for an NMOS 6502. The R65C02 and G65SC02 are; the WDC part is not.
- A chip that runs for a few minutes then fails on a board that hardwires pin 1 to ground is the classic /VP-into-ground failure mode.