Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | Q1 | I/O | Output | CMOS push-pull | Flip-flop 1 Q output. Takes the D1 level on the rising edge of CLOCK1; set high by SET1; reset low by RESET1. |
| 2 | /Q1 | I/O | Output | CMOS push-pull | Flip-flop 1 inverted Q output (/Q). Always the complement of Q1. This is the active low complement of the Q output. |
| 3 | CLOCK1 | Clock / Timing | Input | CMOS, rising edge | Flip-flop 1 clock. Positive-edge triggered: Q1 takes the D1 level on the low-to-high transition. |
| 4 | RESET1 | Control | Input | CMOS, 0 V / VDD, active high | Flip-flop 1 reset. Asynchronous, active HIGH: pulling this pin high forces Q1 low and /Q1 high, regardless of the clock. Must be held low for normal clocked operation. Note: this is active HIGH, the opposite of the 74LS74 active-low clear. |
| 5 | D1 | I/O | Input | CMOS, 0 V / VDD | Flip-flop 1 data input. The level here is transferred to Q1 on the rising edge of CLOCK1. |
| 6 | SET1 | Control | Input | CMOS, 0 V / VDD, active high | Flip-flop 1 set. Asynchronous, active HIGH: pulling this pin high forces Q1 high and /Q1 low, regardless of the clock. Must be held low for normal clocked operation. Note: this is active HIGH, the opposite of the 74LS74 active-low preset. |
| 7 | VSS | Ground | Power | 0 V | Ground return for both flip-flops. |
| 8 | SET2 | Control | Input | CMOS, 0 V / VDD, active high | Flip-flop 2 set. Asynchronous, active HIGH: pulling this pin high forces Q2 high and /Q2 low, regardless of the clock. Must be held low for normal clocked operation. |
| 9 | D2 | I/O | Input | CMOS, 0 V / VDD | Flip-flop 2 data input. The level here is transferred to Q2 on the rising edge of CLOCK2. |
| 10 | RESET2 | Control | Input | CMOS, 0 V / VDD, active high | Flip-flop 2 reset. Asynchronous, active HIGH: pulling this pin high forces Q2 low and /Q2 high, regardless of the clock. Must be held low for normal clocked operation. |
| 11 | CLOCK2 | Clock / Timing | Input | CMOS, rising edge | Flip-flop 2 clock. Positive-edge triggered: Q2 takes the D2 level on the low-to-high transition. |
| 12 | /Q2 | I/O | Output | CMOS push-pull | Flip-flop 2 inverted Q output (/Q). Always the complement of Q2. This is the active low complement of the Q output. |
| 13 | Q2 | I/O | Output | CMOS push-pull | Flip-flop 2 Q output. Takes the D2 level on the rising edge of CLOCK2; set high by SET2; reset low by RESET2. |
| 14 | VDD | Power | Power | +3 V to +15 V | Positive supply. Decouple with 100 nF close to the pin. |
Common uses and repair diagnostics
The CD4013 is the 4000-series CMOS dual D-type flip-flop — two independent flip-flops in a 14-pin DIP, each with its own data, clock, set and reset. The clock is positive-edge triggered; the set and reset are asynchronous and active HIGH, which is the opposite of the 74LS74 whose preset and clear are active low. That polarity difference is the single most important thing to know about this part: a board designed for a 74LS74 expects the preset and clear pins to idle high and assert low, and a CD4013 dropped into that socket idles low and asserts high, so the flip-flops sit permanently set or reset and never clock.
The CD4013 is the CMOS counterpart of the 74LS74, used wherever a board needs to latch a signal on a clock edge or divide a clock by two, but running from a wide or unregulated rail. It builds toggle flip-flops, shift registers and debounce circuits on 9 V and 12 V boards where a TTL part would need a regulated 5 V supply. The asynchronous set and reset are the route to a power-on reset that forces a known state before the first clock edge.
The critical difference from the 74LS74 is the set/reset polarity. The 74LS74 preset and clear are active low — they idle high and assert low. The CD4013 set and reset are active HIGH — they idle low and assert high. The two parts are not pin-compatible in the sense that a board designed for one expects the opposite idle level on the preset/clear pins, and dropping the wrong family in leaves the flip-flops permanently set or reset. The 74HC74 is the CMOS part that shares the 74LS74 pinout and polarity, so reach for that if you need a low-power drop-in for a 74LS74.
- Confirm pin 14 (VDD) is within 3 to 15 V and pin 7 (VSS) is at 0 V. Overvoltage or reversed rails kill CMOS instantly.
- Hold RESET1 and SET1 low (or confirm the board ties them low) and clock CLOCK1: Q1 must take the D1 level on the rising edge. A Q that does not change suggests a dead flip-flop or a floating D input.
- Pull RESET1 high and check Q1 goes low; pull SET1 high and check Q1 goes high. If neither works the asynchronous inputs are damaged. Remember these are active HIGH, the opposite of the 74LS74.
- Check the clock edge is clean and monotonic; a slow or bouncing edge can double-clock the flip-flop.
- If the chip runs warm, suspect a floating input — CMOS should draw microamps at rest.