Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | /OE | Control | Input | TTL, 0 V / 5 V, active low | Output enable, active low. When low, the latched Q outputs drive the bus; when high, the Q outputs are high impedance. The latch itself keeps holding regardless of OE. |
| 2 | 1Q | I/O | Tri-state output | TTL 3-state | Latched output 1. Follows 1D while LE is high; holds the last 1D level when LE is low; high impedance when OE is high. |
| 3 | 1D | I/O | Input | TTL, 0 V / 5 V | Data input 1. |
| 4 | 2D | I/O | Input | TTL, 0 V / 5 V | Data input 2. |
| 5 | 2Q | I/O | Tri-state output | TTL 3-state | Latched output 2. Follows 2D while LE is high; holds when LE is low. |
| 6 | 3Q | I/O | Tri-state output | TTL 3-state | Latched output 3. Follows 3D while LE is high; holds when LE is low. |
| 7 | 3D | I/O | Input | TTL, 0 V / 5 V | Data input 3. |
| 8 | 4D | I/O | Input | TTL, 0 V / 5 V | Data input 4. |
| 9 | 4Q | I/O | Tri-state output | TTL 3-state | Latched output 4. Follows 4D while LE is high; holds when LE is low. |
| 10 | GND | Ground | Power | 0 V | Ground return for all eight latches. |
| 11 | LE | Control | Input | TTL, 0 V / 5 V | Latch enable, level-sensitive. While LE is high the latches are transparent (Q follows D); on the high-to-low transition the latches hold the last D level. This is the pin that distinguishes the 373 from the 374, which uses pin 11 as an edge-triggered clock. |
| 12 | 5Q | I/O | Tri-state output | TTL 3-state | Latched output 5. Follows 5D while LE is high; holds when LE is low. |
| 13 | 5D | I/O | Input | TTL, 0 V / 5 V | Data input 5. |
| 14 | 6D | I/O | Input | TTL, 0 V / 5 V | Data input 6. |
| 15 | 6Q | I/O | Tri-state output | TTL 3-state | Latched output 6. Follows 6D while LE is high; holds when LE is low. |
| 16 | 7Q | I/O | Tri-state output | TTL 3-state | Latched output 7. Follows 7D while LE is high; holds when LE is low. |
| 17 | 7D | I/O | Input | TTL, 0 V / 5 V | Data input 7. |
| 18 | 8D | I/O | Input | TTL, 0 V / 5 V | Data input 8. |
| 19 | 8Q | I/O | Tri-state output | TTL 3-state | Latched output 8. Follows 8D while LE is high; holds when LE is low. |
| 20 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. |
Common uses and repair diagnostics
The 74LS373 is the octal transparent latch with 3-state outputs. While the latch enable (LE) on pin 11 is high, the eight Q outputs follow the eight D inputs transparently; when LE goes low, the Q outputs hold the last D level. The active-low output enable (OE) on pin 1 then gates those latched levels onto a shared bus. It is the part you reach for whenever a multiplexed bus needs to demux an address — the CPU presents the low address byte on the data pins, raises LE to let it through, then drops LE to hold it while the data pins carry data. The 74LS373 occupies the same pin positions as the 74LS374, and the two are a common substitution mistake: the 373 latches on the level of pin 11, the 374 clocks on its rising edge.
The 74LS373 is the address latch on every CPU that multiplexes its address and data buses — the 8085, the 8051, the Z8 and many of the smaller microcontrollers. The CPU presents the low address byte on the data pins, the controller raises LE to let the 74LS373 capture it, then drops LE so the byte stays latched while the data pins switch to carrying data. The 3-state outputs let the same latch sit on a shared bus without contention when the CPU is not driving the address. The 74HC373 and 74HCT373 are the CMOS equivalents and share the same pinout. The 74LS373 and 74LS374 occupy identical pin positions and differ only in what pin 11 does: on the 373 it is a level-sensitive latch enable, on the 374 it is an edge-triggered clock. The two are a common substitution mistake — a 373 in a 374 socket latches continuously instead of on the clock edge, and the captured data is wrong.
- With power off, probe pin 20 (VCC) to pin 10 (GND) for a low-ohms supply rail; a dead short or open points to a decoupling capacitor or the chip itself.
- Power up and check pin 20 sits at 4.75 to 5.25 V. A sagging rail can make a 3-state output float when it should drive, which on a bus looks like a stuck line.
- Drive a D input, raise LE high and check the matching Q follows; drop LE low and check Q holds. A Q that drifts after LE drops means a failed latch cell.
- Toggle OE and check the Q outputs go high impedance when OE is high (read with a pull-up and a pull-down in turn). A Q that drives when OE is high means a failed 3-state buffer.
- If the captured address is wrong, scope LE — a slow edge or a glitch can re-latch the data pins at the wrong time. Confirm the board has the 74LS373 and not the 74LS374 fitted: the two share a pinout but latch on different pin-11 behaviour.