Interactive Connector Diagram
Click or tap any pin in the diagram below to inspect its signal assignment, electrical specification, and wire colour standard.
Click any pin to view its signal assignment, electrical spec, and wire colour.
Supported Systems / Found On — Retro Machine Hubs
This connector is used on the following retro computer systems. Click any colour-coded badge below to open its full board-level repair, diagnostic, and schematic Machine Hub:
Connector Specifications
Connector Pitch
2×25 Contacts, 2.54 mm (0.1") pitch on CPC 464/664 (Centronics 50-pin on German 6128 Schneider)
Pin Orientation
Rear View: Top Row = Odd Pins 1–49 (Right-to-Left); Bottom Row = Even Pins 2–50 (Right-to-Left)
ROM Override
Pull Pin 44 (/ROMDIS) HIGH (+5V) to disable internal IC103 ROM when Pin 43 (/ROMEN) is active-low
RAM Override
Pull Pin 46 (/RAMDIS) HIGH (+5V) to disable internal 64K DRAM when Pin 45 (/RAMRD) is active-low
DDI-1 I/O Ports
Upper ROM Select = #DF00 (ROM 7 = AMSDOS); uPD765A Status/Data = #FB7E / #FB7F; Motor = #FA7E
Full Pin Assignment & Wiring Reference
| Pin | Signal Name | Direction | Electrical Spec / Role | Wire Colour / SCART / Adapter Target |
|---|---|---|---|---|
| 1 / 2 | 1: SOUND | 2: GND | I/O | Pin 1 (Top): Mixed Audio I/O (allows SSA-1/Digiblaster to inject audio) | Pin 2 (Bot): 0V GND | Audio / GND |
| 3 / 4 | 3: A15 | 4: A14 | Out | Z80A Address Bus MSB lines A15 (Top Pin 3) & A14 (Bottom Pin 4) | Address Bus |
| 5 / 6 | 5: A13 | 6: A12 | Out | Z80A Address Bus lines A13 (Top Pin 5) & A12 (Bottom Pin 6) | Address Bus |
| 7 / 8 | 7: A11 | 8: A10 | Out | Z80A Address Bus lines A11 (Top Pin 7) & A10 (Bottom Pin 8) | Address Bus |
| 9 / 10 | 9: A9 | 10: A8 | Out | Z80A Address Bus lines A9 (Top Pin 9) & A8 (Bottom Pin 10) | Address Bus |
| 11 / 12 | 11: A7 | 12: A6 | Out | Z80A Address Bus lines A7 (Top Pin 11) & A6 (Bottom Pin 12) | Address Bus |
| 13 / 14 | 13: A5 | 14: A4 | Out | Z80A Address Bus lines A5 (Top Pin 13) & A4 (Bottom Pin 14) | Address Bus |
| 15 / 16 | 15: A3 | 16: A2 | Out | Z80A Address Bus lines A3 (Top Pin 15) & A2 (Bottom Pin 16) | Address Bus |
| 17 / 18 | 17: A1 | 18: A0 | Out | Z80A Address Bus LSB lines A1 (Top Pin 17) & A0 (Bottom Pin 18) | Address Bus |
| 19 / 20 | 19: D0 | 20: D1 | I/O | Z80A Bidirectional Data Bus D0 (Top Pin 19) & D1 (Bottom Pin 20) | Data Bus |
| 21 / 22 | 21: D2 | 22: D3 | I/O | Z80A Bidirectional Data Bus D2 (Top Pin 21) & D3 (Bottom Pin 22) | Data Bus |
| 23 / 24 | 23: D4 | 24: D5 | I/O | Z80A Bidirectional Data Bus D4 (Top Pin 23) & D5 (Bottom Pin 24) | Data Bus |
| 25 / 26 | 25: NC | 26: NC (Key Slot) | NC | Unconnected / Secondary Keyway Slot position on some connectors | NC |
| 27 / 28 | 27: D6 | 28: /MREQ | I/O | Pin 27 (Top): Data Bit 6 | Pin 28 (Bot): Z80A /MREQ (Active-Low Memory Request) | Data / Control |
| 29 / 30 | 29: D7 | 30: /RFSH | I/O | Pin 29 (Top): Data Bit 7 (MSB) | Pin 30 (Bot): Z80A /RFSH (DRAM Refresh Strobe) | Data / Control |
| 31 / 32 | 31: /RD | 32: /M1 | Out | Pin 31 (Top): Z80A /RD (Read Strobe) | Pin 32 (Bot): /M1 (Machine Cycle 1 / Opcode Fetch) | Control |
| 33 / 34 | 33: /WR | 34: /IORQ | Out | Pin 33 (Top): Z80A /WR (Write Strobe) | Pin 34 (Bot): /IORQ (I/O Request) | Control |
| 35 / 36 | 35: /HALT | 36: PHI (4 MHz) | Out | Pin 35 (Top): Z80A /HALT | Pin 36 (Bot): 4.0 MHz CPU Clock from Gate Array Pin 4 | Clock / Control |
| 37 / 38 | 37: /INT | 38: /NMI | In | Pin 37 (Top): 300 Hz Maskable Interrupt | Pin 38 (Bot): /NMI (Multiface II Stop Button!) | Interrupts |
| 39 / 40 | 39: /BUSRQ | 40: /BUSACK | I/O | Pin 39 (Top): Bus Request Input | Pin 40 (Bot): Bus Acknowledge Output | DMA Control |
| 41 / 42 | 41: /RESET | 42: /READY (WAIT) | I/O | Pin 41 (Top): System /RESET | Pin 42 (Bot): Gate Array READY output to Z80 /WAIT (Pin 24) | Reset / Wait |
| 43 / 44 | 43: /ROMEN | 44: /ROMDIS | I/O | Pin 43 (Top): Gate Array ROM Enable Out | Pin 44 (Bot): Pull HIGH (+5V) to disable internal ROM! | DDI-1 / ROM Board |
| 45 / 46 | 45: /RAMRD | 46: /RAMDIS | I/O | Pin 45 (Top): Gate Array RAM Read Out | Pin 46 (Bot): Pull HIGH (+5V) to disable internal RAM! | 512K RAM Expansion |
| 47 / 48 | 47: CURSOR | 48: LPEN | I/O | Pin 47 (Top): 6845 CRTC Cursor Out (Pin 19) | Pin 48 (Bot): 6845 Lightpen Strobe In (Pin 3) | Video / Lightpen |
| 49 / 50 | 49: GND | 50: +5V DC | Pwr | Pin 49 (Top-Left): 0 V System Ground | Pin 50 (Bottom-Left): +5.0 V DC Regulated Bus Rail | Red (+5V) / Black |
How the DDI-1 Disc Interface, ROM Boards & Diagnostic Cartridges Map Into the CPC 464
The 50-way PCB edge connector on the rear of the Amstrad CPC 464 (and 664/6128) exposes the complete unbuffered Z80A CPU bus plus four Gate Array memory-override signals (`/ROMEN` Pin 43, `/ROMDIS` Pin 44, `/RAMRD` Pin 45, `/RAMDIS` Pin 46) and an analog `SOUND` mix input/output (Pin 1). This allows external peripherals like the Amstrad DDI-1 Floppy Disc Interface (which maps AMSDOS into Upper ROM 7 at `$C000–$FFFF` and the NEC uPD765A FDC at I/O `$FB7E/$FA7E`), dk'tronics 64K/512K RAM expansions, SSA-1 speech synthesizers, and modern M4 / Ulifac / Dandanator DiagROM boards to take full control of the machine.
- Overriding Internal Lower OS ($0000–$3FFF) or Upper BASIC ($C000–$FFFF) ROM: When the Gate Array enables ROM reads, it pulls Pin 43 (/ROMEN) LOW. An external ROM board (or DDI-1 interface when Upper ROM 7 is selected via I/O port #DF00) pulls Pin 44 (/ROMDIS) HIGH (+5V), which forces the Gate Array to keep the internal IC103 ROM chip-select disabled while the external EPROM drives D0–D7!
- Bypassing a Dead Onboard ROM with a Lower-ROM Diagnostic Cartridge: A Dandanator CPC or DiagROM board pulls /ROMDIS (Pin 44) HIGH whenever A15=0 and A14=0 ($0000–$3FFF), replacing the internal Lower OS ROM immediately at Z80 reset ($0000) to test 4164 DRAMs and the 6845 CRTC on a black-screen machine.